1. Field of the Invention
The present invention is in the field of complementary metal oxide semiconductor (CMOS), dynamic random-access memory (DRAM) integrated circuits. More particularly, the present invention relates to a method of making a CMOS DRAM memory circuit chip which includes field effect transistors (FET's), and a capacitor cooperatively defining a memory cell. Each of the FET's is paired with a capacitor to define one memory cell. A binary value (i.e., one or zero) is stored on the memory cell capacitor in the form of stored charge representing a voltage. A comparison charge value equal generally to one-half the voltage level of binary one may be simultaneously stored on a dummy cell capacitor. Thus, the stored value of one or zero can be determined after a time interval either be comparison to a reference voltage value or by comparison of the stored memory cell value to the dummy cell value. When the stored memory cell value is compared to the dummy cell stored value, a positive difference may represent a stored "one", for example, and a negative difference would then be equal to a stored "zero".
2. Related Technology
A conventional CMOS-technology integrated circuit device is known in accord with U.S. Pat. No. 4,435,895 (hereinafter, the '895 patent), issued 13 Mar. 1984, to Louis C. Parrillo, et al., and assigned to Bell Laboratories. The '895 patent is believed to disclose a CMOS-technology integrated circuit having complementary transistors formed in respective P-type and N-type tubs or wells of the integrated circuit. The '895 patent does not teach nor suggest the combination of a capacitor structure with the CMOS integrated circuit. The '895 patent does not teach nor suggest the formation of a DRAM memory cell by structuring a capacitor atop the substrate of the integrated circuit.
Another conventional CMOS-technology integrated circuit is known in accord with U.S. Pat. No. 4,761,384 (hereinafter, the '384 patent), issued 2 Aug. 1988, to Franz Neppl, et al., and assigned to Siemens Ag. The '384 patent is believed to disclose an integrated circuit in which FET's formed in respective N-type and P-type wells are provided with a superior latch-up hardness by use of an out-diffusion process in the formation of the wells. There is no teaching nor suggestion in the '384 patent to combine a capacitor with the FET's in order to define a memory cell. No teaching or suggestion appears in the '384 patent to fabricate a DRAM with capacitors situated atop an oxide layer carried on the substrate of the integrated circuit.
Still another conventional integrated circuit of CMOS type is know in accord with U.S. Pat. No. 5,283,203 (hereinafter, the '203 patent), issued 1 Feb. 1994, to Manzur Gill, et al., and assigned to Texas Instruments. The integrated circuit disclosed by the '203 patent may take the form of a static memory device. Each memory cell of the integrated circuit memory device includes a FET type transistor with a source, a drain, a floating gate, and a control gate. Charge is either stored or is not stored on the floating gate of an FET to produce a corresponding non-conductive or conductance state for the particular FET, which is read as either a stored zero or a stored one, respectively. Reading the stored value state (i.e., either one or zero) of a cell does not destroy the stored value. Thus, the memory is static, as opposed to a dynamic memory (DRAM) in which reading the stored content of a memory cell destroys the content. The memory device of the '203 patent does not include in each memory cell a separate capacitor structure upon which charge is stored, and the stored charge level of which is read by interrogating the cell be closing an associate FET transistor switch to conduct the charge externally of the cell.